Graphene nanomesh may be the semiconductor solution

I’ve done tons of blogging on graphene and this news seems to be direct competition with this graphene news I covered about a week ago. The issue is turning graphene into a semiconductor to allow the material to eventually replace silicon in electronic devices. The last link up there goes to a post outlining the concept of using nanoribbons of graphene, the middle link goes to research claiming a “nanomesh” is a superior method of turning the carbon nanomaterial into a semiconductor.

The release:

New graphene ‘nanomesh’ could change the future of electronics

Graphene, a one-atom-thick layer of a carbon lattice with a honeycomb structure, has great potential for use in radios, computers, phones and other electronic devices. But applications have been stymied because the semi-metallic graphene, which has a zero band gap, does not function effectively as a semiconductor to amplify or switch electronic signals.

While cutting graphene sheets into nanoscale ribbons can open up a larger band gap and improve function, ‘nanoribbon’ devices often have limited driving currents, and practical devices would require the production of dense arrays of ordered nanoribbons — a process that so far has not been achieved or clearly conceptualized.

But Yu Huang, a professor of materials science and engineering at the UCLA Henry Samueli School of Engineering and Applied Science, and her research team, in collaboration with UCLA chemistry professor Xiangfeng Duan, may have found a new solution to the challenges of graphene.

In research to be published in the March issue of Nature Nanotechnology (currently available online), Huang’s team reveals the creation of a new graphene nanostructure called graphene nanomesh, or GNM. The new structure is able to open up a band gap in a large sheet of graphene to create a highly uniform, continuous semiconducting thin film that may be processed using standard planar semiconductor processing methods.

“The nanomeshes are prepared by punching a high-density array of nanoscale holes into a single or a few layers of graphene using a self-assembled block copolymer thin film as the mask template,” said Huang.

The nanomesh can have variable periodicities, defined as the distance between the centers of two neighboring nanoholes. Neck widths, the shortest distance between the edges of two neighboring holes, can be as low as 5 nanometers.

This ability to control nanomesh periodicity and neck width is very important for controlling electronic properties because charge transport properties are highly dependent on the width and the number of critical current pathways.

Using such nanomesh as the semiconducting channel, Huang and her team have demonstrated room-temperature transistors that can support currents nearly 100 times greater than individual graphene nanoribbon devices, but with a comparable on-off ratio. The on-off ratio is the ratio between the currents when a device is switched on or switched off. This usually reveals how effectively a transistor can be switched off and on.

The researchers have also shown that the on-off ratio can be tuned by varying the neck width.

“GNMs can address many of the critical challenges facing graphene, as well as bypass the most challenging assembly problems,” Huang said. “In conjunction with recent advances in the growth of graphene over a large-area substrate, this concept has the potential to enable a uniform, continuous semiconducting nanomesh thin film that can be used to fabricate integrated devices and circuits with desired device size and driving current.

“The concept of the GNM therefore points to a clear pathway towards practical application of graphene as a semiconductor material for future electronics. The unique structural and electronic characteristics of the GNMs may also open up exciting opportunities in highly sensitive biosensors and a new generation of spintronics, from magnetic sensing to storage,” she said.

###

The study was funded in part by Huang’s UCLA Henry Samueli School of Engineering and Applied Science Fellowship.

The UCLA Henry Samueli School of Engineering and Applied Science, established in 1945, offers 28 academic and professional degree programs, including an interdepartmental graduate degree program in biomedical engineering. Ranked among the top 10 engineering schools at public universities nationwide, the school is home to seven multimillion-dollar interdisciplinary research centers in wireless sensor systems, nanotechnology, nanomanufacturing and nanoelectronics, all funded by federal and private agencies.

For more news, visit the UCLA Newsroom and follow us on Twitter.

Graphene replacing silicon — is it “when” and not “if?”

Not quite yet, but headway is being made in making graphene the successor to silicon as the semiconductor for electronics. I first blogged about graphene replacing silicon back in late March 2008 (this blog wasn’t even three months old at the time — hit the link and dig the crazy layout I was using for KurzweilAI posts).

From the first link, the latest news — both good and bad — in making graphene the semiconductor of choice:

“Graphene has been the subject of intense focus and research for a few years now,” Philip Kim tells PhysOrg.com. “There are researchers that feel that it is possible that graphene could replace silicon as a semiconductor in electronics.”

Kim is a scientist at Columbia University in New York City. He has been working with Melinda Han and Juliana Brant to try and come up with a way to make graphene a feasible replacement for silicon. Toward that end, they have been looking at ways to overcome some of the problems associated with using graphene as a semiconductor in electronic devices. They set forth some ideas for electron transport for graphene in Physical Review Letters: “Electron Transport in Disordered Graphene Nanoribbons.”

“Graphene has high mobility, and less scattering than silicon. Theoretically, it is possible to make smaller structures that are more stable at the nanolevel than those made from silicon,” Kim says. He points out that as electronics continue to shrink in size, the interest in finding viable alternatives to silicon is likely to increase. Graphene is a good candidate because of the high electron mobility it offers, its stability on such a small scale, and the possibility that one could come up with different device concepts for electronics.

And here’s a bonus fun graphene graphic from the link:

Graphene is an atomic-scale honeycomb lattice made of carbon atoms. By Dr. Thomas Szkopek, via Wikipedia

DNA scaffolding and circuit boards

A release red hot from the inbox:

IBM Scientists Use DNA Scaffolding To Build Tiny Circuit Boards

Nanotechnology advancement could lead to smaller, faster, more energy efficient computer chips

SAN JOSE, Calif., Aug. 17 /PRNewswire-FirstCall/ — Today, scientists at IBM Research (NYSE:IBM) and the California Institute of Technology announced a scientific advancement that could be a major breakthrough in enabling the semiconductor industry to pack more power and speed into tiny computer chips, while making them more energy efficient and less expensive to manufacture.

  (Photo:  http://www.newscom.com/cgi-bin/prnh/20090817/NY62155-a )
  (Photo:  http://www.newscom.com/cgi-bin/prnh/20090817/NY62155-b )
  (Logo:  http://www.newscom.com/cgi-bin/prnh/20090416/IBMLOGO )

IBM Researchers and collaborator Paul W.K. Rothemund, of the California Institute of Technology, have made an advancement in combining lithographic patterning with self assembly – a method to arrange DNA origami structures on surfaces compatible with today’s semiconductor manufacturing equipment.

Today, the semiconductor industry is faced with the challenges of developing lithographic technology for feature sizes smaller than 22 nm and exploring new classes of transistors that employ carbon nanotubes or silicon nanowires. IBM’s approach of using DNA molecules as scaffolding — where millions of carbon nanotubes could be deposited and self-assembled into precise patterns by sticking to the DNA molecules – may provide a way to reach sub-22 nm lithography.

The utility of this approach lies in the fact that the positioned DNA nanostructures can serve as scaffolds, or miniature circuit boards, for the precise assembly of components – such as carbon nanotubes, nanowires and nanoparticles – at dimensions significantly smaller than possible with conventional semiconductor fabrication techniques. This opens up the possibility of creating functional devices that can be integrated into larger structures, as well as enabling studies of arrays of nanostructures with known coordinates.

“The cost involved in shrinking features to improve performance is a limiting factor in keeping pace with Moore’s Law and a concern across the semiconductor industry,” said Spike Narayan, manager, Science & Technology, IBM Research – Almaden. “The combination of this directed self-assembly with today’s fabrication technology eventually could lead to substantial savings in the most expensive and challenging part of the chip-making process.”

The techniques for preparing DNA origami, developed at Caltech, cause single DNA molecules to self assemble in solution via a reaction between a long single strand of viral DNA and a mixture of different short synthetic oligonucleotide strands. These short segments act as staples – effectively folding the viral DNA into the desired 2D shape through complementary base pair binding. The short staples can be modified to provide attachment sites for nanoscale components at resolutions (separation between sites) as small as 6 nanometers (nm). In this way, DNA nanostructures such as squares, triangles and stars can be prepared with dimensions of 100 – 150 nm on an edge and a thickness of the width of the DNA double helix.

IBM uses traditional semiconductor techniques, the same used to make the chips found in today’s computers, to etch out patterns, creating the lithographic templates for this new approach. Either electron beam or optical lithography are used to create arrays of binding sites of the proper size and shape to match those of individual origami structures. The template materials are chosen to have high selectivity so that origami binds only to the patterns of “sticky patches” and nowhere else.

The paper on this work, “Placement and orientation of DNA nanostructures on lithographically patterned surfaces,” by scientists at IBM Research and the California Institute of Technology will be published in the September issue of Nature Nanotechnology and is currently available at: http://www.nature.com/nnano/journal/vaop/ncurrent/abs/nnano.2009.220.html.

For more information about IBM Research, please visit http://www.research.ibm.com/.

To view and download DNA scaffolding images, in high or low resolution, please go to: http://www.thenewsmarket.com/ibm.

Photo:  http://www.newscom.com/cgi-bin/prnh/20090416/IBMLOGO
http://www.newscom.com/cgi-bin/prnh/20090817/NY62155-b
http://www.newscom.com/cgi-bin/prnh/20090817/NY62155-a
PRN Photo Desk, photodesk@prnewswire.com
Source: IBM
  

Web Site:  http://www.research.ibm.com/

Nanotech improves transistor chips

Nanotechnology offers fairly regular breakthroughs in chip tech. Here’s the latest.

The release:

Self-assembled nanowires could make chips smaller and faster

CHAMPAIGN, Ill. — Researchers at the University of Illinois have found a new way to make transistors smaller and faster. The technique uses self-assembled, self-aligned, and defect-free nanowire channels made of gallium arsenide.

In a paper to appear in the IEEE (Institute of Electrical and Electronics Engineers) journal Electron Device Letters, U. of I. electrical and computer engineering professor Xiuling Li and graduate research assistant Seth Fortuna describe the first metal-semiconductor field-effect transistor fabricated with a self-assembled, planar gallium-arsenide nanowire channel.

Nanowires are attractive building blocks for both electronics and photonics applications. Compound semiconductor nanowires, such as gallium arsenide, are especially desirable because of their better transport properties and versatile heterojunctions. However, a number of challenges – including integration with existing microelectronics – must first be overcome.

“Our new planar growth process creates self-aligned, defect-free gallium-arsenide nanowires that could readily be scaled up for manufacturing purposes,” said Li, who also is affiliated with the university’s Micro and Nanoelectronics Laboratory and the Beckman Institute. “It’s a non-lithographic process that can precisely control the nanowire dimension and orientation, yet is compatible with existing circuit design and fabrication technology.”

The gallium-arsenide nanowire channel used in the researchers’ demonstration transistor was grown by metal organic chemical vapor deposition using gold as a catalyst. The rest of the transistor was made with conventional microfabrication techniques.

While the diameter of the transistor’s nanowire channel was approximately 200 nanometers, nanowires with diameters as small as 5 nanometers can be made with the gold-catalyzed growth technique, the researchers report. The self-aligned orientation of the nanowires is determined by the crystal structure of the substrate and certain growth parameters.

In earlier work, Li and Fortuna demonstrated they could grow the nanowires and then transfer-print them on other substrates, including silicon, for heterogeneous integration. “Transferring the self-aligned planar nanowires while maintaining both their position and alignment could enable flexible electronics and photonics at a true nanometer scale,” the researchers wrote in the December 2008 issue of the journal Nano Letters.

In work presented in the current paper, the researchers grew the gallium-arsenide nanowire channel in place, instead of transferring it. In contrast to the common types of non-planar gallium arsenide nanowires, the researchers’ planar nanowire was free from twin defects, which are rotational defects in the crystal structure that decrease the mobility of the charge carriers.

“By replacing the standard channel in a metal-semiconductor field-effect transistor with one of our planar nanowires, we demonstrated that the defect-free nanowire’s electron mobility was indeed as high as the corresponding bulk value,” Fortuna said. “The high electron mobility nanowire channel could lead to smaller, better and faster devices.”

Considering their planar, self-aligned and transferable nature, the nanowire channels could help create higher performance transistors for next-generation integrated circuit applications, Li said.

The high quality planar nanowires can also be used in nano-injection lasers for use in optical communications.

The researchers are also developing new device concepts driven by further engineering of the planar one-dimensional nanostructure.

 

###

 

The work was supported by the National Science Foundation.

Is graphene going to be the new semiconductor?

Here’sa report from PhysOrg on graphene replacing semiconductors in the next generation computer chip:

When one looks at the structure of graphite, stacked layers of pure carbon are apparent. However, it wasn’t until 2004 that a process sophisticated enough to “slice” off one of the layers was discovered. This single layer is called graphene. Graphene is basically a sheet of bonded carbon atoms, with the thickness of only one atom. If one could look down at graphene from the top, one would observe that the sheet bears a strong resemblance to honeycomb, with its hexagons fitted snugly together.

“Graphene behaves almost like semiconductor but without a energy gap,” Kim explains. This is why it would do well as a material for computer chips. “When you apply an electric field perpendicular to graphene, the number of electrons – the carrier density – can be tuned.”

“One of the main themes is how fast the charge can move in graphene,” Kim continues. “Higher mobility means electron conducts faster in the system. It has always been speculated that the mobility of graphene can be quite high. But it has not been shown as high as some of the highest semiconductors in the past.”

Conductive plastics

A potentially very useful nanotech application. Putting two insulating plastics together creates a two nanometer electrically conductive strip. This interface is more conductive than standard semiconductors.

From the link:

Jamming the right two pieces of plastic together creates a thin but strongly conducting channel along the junction that acts like a metal, say Dutch researchers. The discovery could lead to a whole new way of making electronics from non-metallic materials, and even new superconductors.

Alberto Morpurgo’s team at Delft University of Technology in the Netherlands attached a micrometer-thick crystal of the organic polymer TTF to a similarly thin organic crystal of the polymer TCNQ.

The thin, flexible crystals conform to each other’s shape and stick together due to van der Waals forces, says Morpurgo.

Metal surprise

Both TTF and TCNQ are electrical insulators. But Morpurgo’s team found that a 2-nanometre-thick strip along the interface between the two crystals conducts electricity as well as a metal.

(Hat tip: KurzweilAI.net)

NIST preps bridge to molecular electronics

From KurzweilAI.net:

NIST team proves bridge from conventional to molecular electronics possible

KurzweilAI.net, March 19, 2008Researchers at the National Institute of Standards and Technology (NIST) have set the stage for building an “evolutionary link” between the microelectronics of today (built from semiconductor compounds) and future generations of devices, made largely from complex organic molecules, by assembling the devices on the same kind of substrate used in conventional microchips. Side and top view of NIST molecular resistor The ability to use a silicon crystal substrate compatible with the industry-standard CMOS (complementary metal oxide semiconductor) manufacturing technology paves the way for hybrid CMOS-molecular device circuitry. This, in turn, is a necessary precursor to a “beyond CMOS” totally molecular technology. National Institute of Standards and Technology News Release