David Kirkpatrick

September 10, 2009

Graphite, data storage and semiconductors

Interesting release from Rice involving graphite and nanotechnology, but not the usual carbon nanotubes, graphene or graphane.

The release:

Graphitic memory techniques advance at Rice

Researchers simplify fabrication of nano storage, chip-design tools

Advances by the Rice University lab of James Tour have brought graphite’s potential as a mass data storage medium a step closer to reality and created the potential for reprogrammable gate arrays that could bring about a revolution in integrated circuit logic design.

In a paper published in the online journal ACS Nano, Tour and postdoctoral associate Alexander Sinitskii show how they’ve used industry-standard lithographic techniques to deposit 10-nanometer stripes of amorphous graphite, the carbon-based, semiconducting material commonly found in pencils, onto silicon. This facilitates the creation of potentially very dense, very stable nonvolatile memory for all kinds of digital devices.

With backing from a major manufacturer of memory chips, Tour and his team have pushed the technology forward in several ways since a paper that appeared last November first described two-terminal graphitic memory. While noting advances in other molecular computing techniques that involve nanotubes or quantum dots, he said none of those have yet proved practical in terms of fabrication.

Not so with this simple-to-deposit graphite. “We’re using chemical vapor deposition and lithography — techniques the industry understands,” said Tour, Rice’s Chao Professor of Chemistry and a professor of mechanical engineering and materials science and of computer science. “That makes this a good alternative to our previous carbon-coated nanocable devices, which perform well but are very difficult to manufacture.”

Graphite makes a good, reliable memory “bit” for reasons that aren’t yet fully understood. The lab found that running a current through a 10-atom-thick layer of graphite creates a complete break in the circuit — literally, a gap in the strip a couple of nanometers wide. Another jolt repairs the break. The process appears to be indefinitely repeatable, which provides addressable ones and zeroes, just like today’s flash memory devices but at a much denser scale.

Graphite’s other advantages were detailed in Tour’s earlier work: the ability to operate with as little as three volts, an astoundingly high on/off ratio (the amount of juice a circuit holds when it’s on, as opposed to off) and the need for only two terminals instead of three, which eliminates a lot of circuitry. It’s also impervious to a wide temperature range and radiation; this makes it suitable for deployment in space and for military uses where exposure to temperature extremes and radiation is a concern.

Tour’s graphite-forming technique is well-suited for other applications in the semiconductor industry. One result of the previous paper is a partnership between the Tour group and NuPGA (for “new programmable gate arrays”), a California company formed around the research to create a new breed of reprogrammable gate arrays that could make the design of all kinds of computer chips easier and cheaper.

The Tour lab and NuPGA, led by industry veteran Zvi Or-Bach (founder of eASIC and Chip Express), have applied for a patent based on vertical arrays of graphite embedded in “vias,” the holes in integrated circuits connecting the different layers of circuitry. When current is applied to a graphite-filled via, the graphite alternately splits and repairs itself (a process also described in the latest paper), just like it does in strip form. Essentially, it becomes an “antifuse,” the basic element of one type of field programmable gate array (FPGA), best described as a blank computer chip that uses software to rewire the hardware.

Currently, antifuse FPGAs can be programmed once. But this graphite approach could allow for the creation of FPGAs that can be reprogrammed at will. Or-Bach said graphite-based FPGAs would start out as blanks, with the graphite elements split. Programmers could “heal” the antifuses at will by applying a voltage, and split them with an even higher voltage.

Such a device would be mighty handy to computer-chip designers, who now spend many millions to create the photolithography mask sets used in chip fabrication. If the design fails, it’s back to square one.

“As a result of that, people are only hesitantly investing in new chip designs,” said Tour. “They stick with the old chip designs and make modifications. FPGAs are chips that have no specific ability, but you use software to program them by interconnecting the circuitry in different ways.”  That way, he said, fabricators don’t need expensive mask sets to try new designs.

“The No. 1 problem in the industry, and one that gives an opportunity for a company like ours, is that the cost of masks keeps moving up as people push semiconductors into future generators,” said Or-Bach. “Over the last 10 years, the cost of a mask set has multiplied almost 10 times.

“If we can really make something that will be an order of magnitude better, the markets will be happy to make use of it. That’s our challenge, and I believe the technology makes it possible for us to do that.”

The ACS Nano paper appears here: http://pubs.acs.org/doi/pdf/10.1021/nn9006225

Read more about Tour’s research of graphitic memory here: 
http://www.media.rice.edu/media/NewsBot.asp?MODE=VIEW&ID=11817

To download images, go here: http://www.rice.edu/nationalmedia/images/graphitestripes.jpg
http://www.rice.edu/nationalmedia/images/graphitestripes2.jpg
http://www.rice.edu/nationalmedia/images/vias.jpg

December 20, 2008

Nanotube integrated circuits

Filed under: Science, Technology — Tags: , , , , — David Kirkpatrick @ 4:50 pm

Built on introduced flaws in the nanotubes themselves. This research was published in ACS Nano (abstract).

From the Nanodot link:

Computational nanotech studies have shown that deliberate introduction of structural defects at specific sites in carbon nanotubes can guide electrons along specific paths, providing a way to fabricate complex electronic circuits from nanotubes. Although this research was theoretical, the researchers are quoted as saying focused electron beams could be used to create the defects where they would be needed to make complicated networks. An item on KurzweilAI.net led to this article on New Scientist Tech, written by Colin Barras. From “Flawed nanotubes could be perfect silicon replacement“:

The paradox of perfection — that flaws make things perfect — could be the key to designing nanoelectronic circuits from carbon nanotubes, according to US scientists.

They have discovered that a circuit of nanotubes can only guide a current if some of the tubes carry structural defects.

Individual carbon nanotubes are exceptionally good conductors because they are essentially a single carbon molecule. They can even outdo silicon at transmitting charge, which means nanotube circuits could boost computing speeds while reducing chip size…

August 13, 2008

All-nanowire loaded chip

Just after blogging on UC Berkeley’s recent research gift from Applied Materials, this story appears in the inbox. The university has created the first integrated circuit using nanowires as both sensors and electronic components.

This technology has a lot of possibities, even beyond silicon chips.

From the second link:

Nanowires make good sensors because their small dimensions enhance their sensitivity. Nanowire-based light sensors, for example, can detect just a few photons. But to be useful in practical devices, the sensors have to be integrated with electronics that can amplify and process such small signals. This has been a problem, because the materials used for sensing and electronics cannot easily be assembled on the same surface. What’s more, a reliable way of aligning the tiny nanowires that could be practical on a large scale has been hard to come by.

A printing method developed by the Berkeley group could solve both problems. First, the researchers deposit a polymer on a silicon substrate and use lithography to etch out patterns where the optical sensing nanowires should be. They then print a single layer of cadmium selenide nanowires over the pattern; removing the polymer leaves only the nanowires in the desired location for the circuit. They repeat the process with the second type of nanowires, which have germanium cores and silicon shells and form the basis of the transistors. Finally, they deposit electrodes to complete the circuits.

University of California, Berkeley, researchers were able to create an orderly circuit array from two types of tiny nanowires, which can function as optical sensors and transistors. Each of the circuits on the 13-by-20 array serves as a single pixel in an all-nanowire image sensor.

Squared away: University of California, Berkeley, researchers were able to create an orderly circuit array from two types of tiny nanowires, which can function as optical sensors and transistors. Each of the circuits on the 13-by-20 array serves as a single pixel in an all-nanowire image sensor.

July 7, 2008

Building a better heat sink and mass producing nanotube circuits

From KurzweilAI.net — amazing advances in chip-cooling tech removes 1K watts per square centimeter and nanotube-laden integrated circuits become economical.

Chip-cooling Technology Achieves ‘Dramatic’ 1,000-watt Capacity
Science Daily, July 2, 2008

Purdue University researchers have developed a technology that uses “microjets” to deposit liquid into tiny channels and remove five times more heat (1,000 watts per square centimeter) than other experimental high-performance chip-cooling methods for computers and electronics.

 
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Engineers show nanotube circuits can be made en masse
Nanowerk News, July 4, 2008

Stanford electrical engineers have developed a method for making integrated circuit chips with the needed variety of logic gates on the scale and with the parallelism that the semiconductor industry must employ to make chips that are economical.

The Stanford-devised process involves growing nanotubes on a quartz wafer and then transferring them onto a silicon wafer patterned with metal electrodes. The nanotubes could then connect the electrodes to make transistors and logic gates.

 
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