David Kirkpatrick

March 11, 2010

The dice roll of multiple-processor computers

Garbage-in/garbage-out may be a computing truism, but getting the same result after entering the same commands ought to be a given. I didn’t realize this was even an issue with multiple-processor computers.

The release:

Conquering the chaos in modern, multiprocessor computers

Computers should not play dice. That, to paraphrase Einstein, is the feeling of a University of Washington computer scientist with a simple manifesto: If you enter the same computer command, you should get back the same result. Unfortunately, that is far from the case with many of today’s machines. Beneath their smooth exteriors, modern computers behave in wildly unpredictable ways, said Luis Ceze, a UW assistant professor of computer science and engineering.

“With older, single-processor systems, computers behave exactly the same way as long as you give the same commands. Today’s computers are non-deterministic. Even if you give the same set of commands, you might get a different result,” Ceze said.

He and UW associate professors of computer science and engineering Mark Oskin and Dan Grossman and UW graduate students Owen Anderson, Tom Bergan, Joseph Devietti, Brandon Lucia and Nick Hunt have developed a way to get modern, multiple-processor computers to behave in predictable ways, by automatically parceling sets of commands and assigning them to specific places. Sets of commands get calculated simultaneously, so the well-behaved program still runs faster than it would on a single processor.

Next week at the International Conference on Architectural Support for Programming Languages and Operating Systems (http://www.ece.cmu.edu/CALCM/asplos10/doku.php) in Pittsburgh, Bergan will present a software-based version of this system that could be used on existing machines. It builds on a more general approach the group published last year, which was recently chosen as a top paper for 2009 by the Institute of Electrical and Electronics Engineers’ journal Micro.

In the old days one computer had one processor. But today’s consumer standard is dual-core processors, and even quad-core machines are appearing on store shelves. Supercomputers and servers can house hundreds, even thousands, of processing units.

On the plus side, this design creates computers that run faster, cost less and use less power for the same performance delivered on a single processor. On the other hand, multiple processors are responsible for elusive errors that freeze Web browsers and crash programs.

It is not so different from the classic chaos problem in which a butterfly flaps its wings in one place and can cause a hurricane across the globe. Modern shared-memory computers have to shuffle tasks from one place to another. The speed at which the information travels can be affected by tiny changes, such as the distance between parts in the computer or even the temperature of the wires. Information can thus arrive in a different order and lead to unexpected errors, even for tasks that ran smoothly hundreds of times before.

“With multi-core systems the trend is to have more bugs because it’s harder to write code for them,” Ceze said. “And these concurrency bugs are much harder to get a handle on.”

One application of the UW system is to make errors reproducible, so that programs can be properly tested.

“We’ve developed a basic technique that could be used in a range of systems, from cell phones to data centers,” Ceze said. “Ultimately, I want to make it really easy for people to design high-performing, low-energy and secure systems.”

Last year Ceze, Oskin, and Peter Godman, a former director at Isilon Systems, founded a company to commercialize their technology. PetraVM (http://petravm.com/) is initially named after the Greek word for rock because it hopes to develop “rock-solid systems,” Ceze said. The Seattle-based startup will soon release its first product, Jinx, which makes any errors that are going to crop up in a program happen quickly.

“We can compress the effect of thousands of people using a program into a few minutes during the software’s development,” Ceze said. “We want to allow people to write code for multi-core systems without going insane.”

The company already has some big-name clients trying its product, Ceze said, though it is not yet disclosing their identities.

“If this erratic behavior irritates us, as software users, imagine how it is for banks or other mission-critical applications.”

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Part of this research was funded by the National Science Foundation and a Microsoft Research fellowship.

More information on the research is at http://sampa.cs.washington.edu.

April 23, 2009

Nanotech improves transistor chips

Nanotechnology offers fairly regular breakthroughs in chip tech. Here’s the latest.

The release:

Self-assembled nanowires could make chips smaller and faster

CHAMPAIGN, Ill. — Researchers at the University of Illinois have found a new way to make transistors smaller and faster. The technique uses self-assembled, self-aligned, and defect-free nanowire channels made of gallium arsenide.

In a paper to appear in the IEEE (Institute of Electrical and Electronics Engineers) journal Electron Device Letters, U. of I. electrical and computer engineering professor Xiuling Li and graduate research assistant Seth Fortuna describe the first metal-semiconductor field-effect transistor fabricated with a self-assembled, planar gallium-arsenide nanowire channel.

Nanowires are attractive building blocks for both electronics and photonics applications. Compound semiconductor nanowires, such as gallium arsenide, are especially desirable because of their better transport properties and versatile heterojunctions. However, a number of challenges – including integration with existing microelectronics – must first be overcome.

“Our new planar growth process creates self-aligned, defect-free gallium-arsenide nanowires that could readily be scaled up for manufacturing purposes,” said Li, who also is affiliated with the university’s Micro and Nanoelectronics Laboratory and the Beckman Institute. “It’s a non-lithographic process that can precisely control the nanowire dimension and orientation, yet is compatible with existing circuit design and fabrication technology.”

The gallium-arsenide nanowire channel used in the researchers’ demonstration transistor was grown by metal organic chemical vapor deposition using gold as a catalyst. The rest of the transistor was made with conventional microfabrication techniques.

While the diameter of the transistor’s nanowire channel was approximately 200 nanometers, nanowires with diameters as small as 5 nanometers can be made with the gold-catalyzed growth technique, the researchers report. The self-aligned orientation of the nanowires is determined by the crystal structure of the substrate and certain growth parameters.

In earlier work, Li and Fortuna demonstrated they could grow the nanowires and then transfer-print them on other substrates, including silicon, for heterogeneous integration. “Transferring the self-aligned planar nanowires while maintaining both their position and alignment could enable flexible electronics and photonics at a true nanometer scale,” the researchers wrote in the December 2008 issue of the journal Nano Letters.

In work presented in the current paper, the researchers grew the gallium-arsenide nanowire channel in place, instead of transferring it. In contrast to the common types of non-planar gallium arsenide nanowires, the researchers’ planar nanowire was free from twin defects, which are rotational defects in the crystal structure that decrease the mobility of the charge carriers.

“By replacing the standard channel in a metal-semiconductor field-effect transistor with one of our planar nanowires, we demonstrated that the defect-free nanowire’s electron mobility was indeed as high as the corresponding bulk value,” Fortuna said. “The high electron mobility nanowire channel could lead to smaller, better and faster devices.”

Considering their planar, self-aligned and transferable nature, the nanowire channels could help create higher performance transistors for next-generation integrated circuit applications, Li said.

The high quality planar nanowires can also be used in nano-injection lasers for use in optical communications.

The researchers are also developing new device concepts driven by further engineering of the planar one-dimensional nanostructure.

 

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The work was supported by the National Science Foundation.