David Kirkpatrick

July 3, 2008

Solar moratorium news, nanowire memory and tiny, tiny computer chips

From KurzweilAI.net — the US government comes to its senses on the solar moratorium, breakthroughs in nanowire memory, and computer chips heading toward smaller than 10 nanometers.

U.S. Lifts Moratorium on New Solar Projects
New York Times, July 3, 2008

Under increasing public pressure over its decision to temporarily halt all new solar development on public land, the Bureau of Land Management said Wednesday that it was lifting the freeze, barely a month after it was put into effect.

See also: Citing Need for Assessments, U.S. Freezes Solar Energy Projects

 
Read Original Article>>

 

New Nanowire-Based Memory Could Beef Up Information Storage
PhysOrg.com, July 2, 2008

University of Pennsylvania researchers have created a type of nanowire-based information storage device that is capable of storing three bit values rather than the usual two.

This ability could lead to a new generation of high-capacity information storage for electronic devices.

The phase changes are achieved by subjecting the nanowires to pulsed electric fields. This process heats the nanowires, altering the core and shell structure from crystalline (ordered) to amorphous (disordered). These two states correspond to two different electrical resistances.

The third value corresponds to the case where the core is amorphous while the shell is crystalline (or visa versa), resulting in an intermediate resistance.

Creating information storage from nanowires can be done via “bottom-up” approaches, using the natural tendency of tiny structures to self-assemble into larger structures, so they may be able to break free of the limitations faced by traditional “top-down” methods, such as patterning a circuit onto a silicon wafer by depositing a nanowire thin film.

 
Read Original Article>>

 

Intel’s Gelsinger Sees Clear Path To 10nm Chips
ChannelWeb, June 30, 2008

Intel sees a “clear way” to manufacturing chips under 10 nanometers, according to Pat Gelsinger, VP of Intel’s Digital Enterprise Group.

The next die shrink milestone will be the 32nm process, set to kick off next year, followed by 14nm a few years after that and then sub-10nm, he said.

 
Read Original Article>>

Leave a Comment »

No comments yet.

RSS feed for comments on this post. TrackBack URI

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

%d bloggers like this: